Method for Reading Data Stored in a Flash Memory According to a Threshold Voltage Distribution and Memory Controller and System Thereof

ABSTRACT

A method for reading data stored in a flash memory is disclosed. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The disclosed embodiments of the present invention relate to readingdata stored in a flash memory, and more particularly, to a method andmemory controller for reading data stored in a flash memory by referringto binary digit distribution characteristics of bit sequences read frommemory cells of the flash memory.

2. Description of the Prior Art

Flash memory can be electrically erased and programmed for data storage.It is widely used in memory cards, solid-state drives, portablemultimedia players, etc. As the flash memory is a non-volatile memory,no power is needed to maintain the information stored in the flashmemory. Besides, the flash memory offers fast read access and bettershock resistance. These characteristics explain the popularity of theflash memory.

The flash memories may be categorized into NOR-type flash memories andNAND-type flash memories. Regarding the NAND flash memory, it hasreduced erasing and programming time and requires less chip area percell, thus allowing greater storage density and lower cost per bit thanthe NOR flash memory. In general, the flash memory stores data in anarray of memory cells made from floating-gate transistors. Each memorycell can store one bit of information or more than one bit ofinformation by adequately controlling the number of electrical charge onits floating gate to configure the threshold voltage required forturning on the memory cell made of a floating-gate transistor. In thisway, when one or more predetermined control gate voltages are applied toa control gate of the floating-gate transistor, the conductive status ofthe floating-gate transistor would indicate the binary digit(s) storedby the floating-gate transistor.

However, due to certain factors, the number of electrical chargeoriginally stored on one flash memory cell may be affected/disturbed.For example, the interference presented in the flash memory may beoriginated from write (program) disturbance, read disturbance, and/orretention disturbance. Taking a NAND flash memory including memory cellseach storing more than one bit of information for example, one physicalpage includes multiple logical pages, and each of the logical pages isread by using one or more control gate voltages. For instance, regardingone flash memory cell which is configured to store three bits ofinformation, the flash memory cell may have one of eight possible states(i.e., electrical charge levels) corresponding to different electricalcharge amounts (i.e., different threshold voltages), respectively.However, due to the increase of the program/erase (P/E) count and/or theretention time, the threshold voltage distribution of memory cells inthe flash memory may be changed. Thus, using original control gatevoltage setting (i.e., threshold voltage setting) to read the storedbits from the memory cell may fail to obtain the correct storedinformation due to the changed threshold voltage distribution.

SUMMARY OF THE INVENTION

In accordance with exemplary embodiments of the present invention, amethod, memory controller, and system for reading data stored in a flashmemory by referring to threshold voltage distribution are proposed tosolve the above-mentioned problem.

According to an aspect of the present invention, an exemplary method forreading data stored in a flash memory is disclosed. The flash memorycomprises a plurality of memory cells and each memory cell has aparticular threshold voltage The exemplary method includes: obtaining afirst threshold voltage distribution representing threshold voltages ofa first group of the memory cells; obtaining a second threshold voltagedistribution representing threshold voltages of a second group of thememory cells, wherein the second threshold voltage distribution isdifferent from the first threshold voltage distribution, and the firstgroup of the memory cells comprises at least a part of the second groupof the memory cells; and controlling the flash memory to perform atleast one read operation upon the first group of the memory cellsaccording to the second threshold voltage distribution.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a memory system according to anexemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating the adjustment made to the control gatevoltage used for reading LSB data according to an embodiment of thepresent invention.

FIG. 3 is a diagram illustrating the operation of determining a shiftingdirection of the control gate voltage for finding a better control gatevoltage used for reading LSB data according to an embodiment of thepresent invention.

FIG. 4 is a diagram illustrating the adjustment made to the control gatevoltage used for reading LSB data according to another embodiment of thepresent invention.

FIG. 5 is a diagram illustrating the adjustment made to the control gatevoltage used for reading LSB data of the target physical page P_1according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating the operation of determining a shiftingdirection of the control gate voltage for finding a better control gatevoltage used for reading LSB data the target physical page P_1 accordingto an embodiment of the present invention.

FIG. 7A is a diagram illustrating the adjustment made to the controlgate voltage used for reading LSB data according to an embodiment of thepresent invention.

FIG. 7B is a diagram showing a threshold voltage distribution obtainedfrom averaging the threshold voltage distribution shown in FIG. 7A.

FIG. 7C is a diagram showing a threshold voltage distribution obtainedfrom selecting a part of information of the threshold voltagedistribution shown in FIG. 7A.

FIG. 8 is a flow chart illustrating a concept of the present invention.

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claimsto refer to particular components. As one skilled in the art willappreciate, manufacturers may refer to a component by different names.This document does not intend to distinguish between components thatdiffer in name but not function. In the following description and in theclaims, the terms “include” and “comprise” are used in an open-endedfashion, and thus should be interpreted to mean “include, but notlimited to . . . ”. Also, the term “couple” is intended to mean eitheran indirect or direct electrical connection. Accordingly, if one deviceis coupled to another device, that connection may be through a directelectrical connection, or through an indirect electrical connection viaother devices and connections.

The generalized conception of the present invention is to read datastored in a flash memory. The flash memory comprises a plurality ofmemory cells, and each memory cell has a particular threshold voltage.The data is read by obtaining a first threshold voltage distributionrepresenting threshold voltages of a first group of the memory cells,obtaining a second threshold voltage distribution representing thresholdvoltages of a second group of the memory cells, wherein the secondthreshold voltage distribution is different from the first thresholdvoltage distribution and the first group of the memory cells comprisesat least a part of the second group of the memory cells, and controllingthe flash memory to perform at least one read operation upon the firstgroup of the memory cells according to the second threshold voltagedistribution. Thereby, a better threshold voltage can be utilized duringthe read operation, and the bit error rate can be reduced. Furtherdetails are described as follows.

Please note that the threshold voltage distribution illustrated in theaccompanying figures and values of the control gate voltages mentionedhereinafter are for illustrative purposes only, and are not meant to belimitations of the present invention. Besides, for simplicity andclarity, reading multiple bits stored by memory cells of one physicalpage in a NAND-type flash memory is taken as an example for illustratingtechnical features of the present invention. However, no matter whetherthe flash memory is a NAND-type flash memory or a flash memory of othertype (e.g., a NOR-type flash memory), the spirit of the presentinvention is obeyed as long as the read operation can be performedaccording to a smoother threshold voltage distribution.

Please refer to FIG. 1, which is a diagram illustrating a memory systemaccording to an exemplary embodiment of the present invention. Theexemplary memory system 1000 includes a memory controller 1200 and theaforementioned flash memory (e.g., a NAMD-type flash memory) 1100. Toread the data stored in the memory cells M_0-M_K of the target physicalpage P_0, the control gate voltages VG_0-VG_N should be properly set.For example, the control gate voltages VG_1-VG_N should be properly setto ensure that all of the memory cells (floating-gate transistors) 103of the physical pages P_1-P_N are conductive. In a case where each ofthe memory cell 103 is configured to store N bits (e.g., three bitsincluding a least significant bit (LSB), a central significant bit(CSB), and a most significant bit (MSB)), the flash memory 102 sets thecontrol gate voltage VG_0 to (2^(N)−1) voltage levels for identifyingall of the N bits of each memory cell 103 of the target physical pageP_0. Each of the memory cells 1110 in this exemplary embodiment isconfigured to store 3 bits, including a least significant bit (LSB), acentral significant bit (CSB), and a most significant bit (MSB). Thus,the memory controller 1200 determines eight control gate voltagesV_(LSB), V_(CSB1), V_(CSB2), V_(MSB1), V_(MSB2), V_(MSB3), and V_(MSB4),and controls the flash memory 1100 to perform read operations accordingto these configured control gate voltages. In the following exemplaryembodiments, read operations are performed upon the LSB of the memorycells. However, this is for illustration purpose only rather than alimitation.

The memory controller 1200 is implemented to control access (read/write)of the flash memory 1100. In this exemplary embodiment, the memorycontroller 1200 includes, but is not limited to, a control logic 1210having a control unit 1212, a counting unit 1214, and a comparing unit1216 included therein, a receiving circuit 1220 having a storage device(e.g., a memory device) 1222, and an ECC circuit 1230 having an ECCdetector 1222 and an ECC corrector 1224 included therein. Please notethat only the elements pertinent to the technical features of thepresent invention are shown in FIG. 1 for clarity and simplicity. Thatis, the memory controller 1200 may include additional elements tosupport other functionality. As mentioned above, the threshold voltagedistribution of memory cells 1110 included in the flash memory 1100 maybe changed due to certain factors such as read disturbance,write/program disturbance, and/or retention disturbance. As known tothose skilled in the art, part of the memory cells 1110 of one physicalpage is utilized for storing ECC information (e.g., an ECC code). Thus,the ECC circuit 1230 is operative to perform an ECC operation upon thereadout information (e.g., a codeword) read from one physical page. Morespecifically, the ECC detector 1222 checks the correctness of thereadout information, thereby detecting the existence of error bitspresented in the checked readout information. When notified by the ECCdetector 1222, the ECC corrector 1224 is operative for correcting theerror bits found in the checked readout information. However, when thenumber of error bits existing in the readout information exceeds amaximum number of error bits that can be corrected by the ECC corrector1224, the ECC corrector 1224 indicates that the readout informationincludes uncorrectable error bits. Thus, the control logic 1210 enablesthe threshold voltage tracking mechanism to determine the readoutinformation which can pass the ECC parity check performed by the ECCcircuit 1230. Detailed are described as below.

In this exemplary embodiment, the ECC circuit 1230 may be aBose-Chaudhuri-Hocquenghem (BCH) decoder. The control logic 1210 isarranged for controlling the flash memory 1100 to perform a plurality ofread operations upon each of the memory cells M_0-M_K of the targetphysical page P_0, and determining readout information of the memorycells M_0-M_K according to binary digit distribution characteristics ofbit sequences BS_0-BS_K. The read operations include at least a firstread operation, a second read operation, and a third read operation usedfor determining control gate voltage shifting direction(s) used forfinding better control gate voltage(s). Further details are described asbelow.

Please refer to FIG. 2 in conjunction with FIG. 3. FIG. 2 is a diagramillustrating the adjustment made to the control gate voltage used forreading LSB data according to an embodiment of the present invention.FIG. 3 is a diagram illustrating the operation of determining a shiftingdirection of the control gate voltage for finding a better control gatevoltage used for reading LSB data according to an embodiment of thepresent invention. Due to change of the threshold voltage distribution,the threshold voltages of some memory cells each originally programmedto store LSB=1 are distributed in the voltage region V5-V9, and thethreshold voltages of some memory cells each originally programmed tohave the electrical charge level L4 to store LSB=0 are distributed inthe voltage region V1-V5. To have a minimum number of error bitspresented in the readout information of the target physical page P_0,the control gate voltage for reading LSB data should be preferably setby V5 shown in FIG. 2. When the initial control gate voltage V_(LSB) isset to V7 by the control unit 1212 and the flash memory 1100 performsthe first read operation upon memory cells M_0-M_K according to theinitial control gate voltage V_(LSB), the number of error bits presentedin the readout information (i.e., a first codeword CW_1 consisted offirst bits of the bit sequences BS_0-BS_K) exceeds the maximum number oferror bits that can be corrected by the ECC circuit 1230. Thus, thethreshold voltage tracking mechanism is enabled accordingly. Next, thecontrol unit 1212 updates the initial control gate voltage V_(LSB)employed by the first read operation by V6 which is lower than V7 with aminimum step size (ΔV) that the memory controller 1200 can control theflash memory 1100 to adjust. Then the control unit 1212 controls theflash memory to perform the second read operation upon memory cellsM_0-M_K according to the updated control gate voltage V_(LSB′). Thus, asecond codeword CW_2 consisted of second bits of the bit sequencesBS_0-BS_K is received by the receiving circuit 1220. Please note thatthe first codeword CW_1 is buffered in the storage device 1222, and bitsof the first codeword CW_1 buffered in the storage device 1222 aretransmitted to the comparing unit 1216 one by one before overwritten bythe incoming bits of the second codeword CW_2. The comparing unit 1216is arranged for comparing bits of the first codeword CW_1 (i.e., firstbits of the bit sequences BS_0-BS_K) and bits of the second codewordCW_2 (i.e., second bits of the bit sequences BS_0-BS_K). The comparisonresult will indicate which bit position has one first bit flipping dueto a transition from a first binary digit (e.g., “1”) to a second binarydigit (e.g., “0”). The counting unit 1214 is coupled to the comparingunit 1216 and the control unit 1212, and is arranged for counting thenumber of first bit flipping between the first codeword CW_1 and thesecond codeword CW_2. That is, the counting unit 1214 generates a firstcounter number N1 by counting the number of first bit flipping betweenfirst bits and second bits of the bit sequences BS_0-BS_K, wherein onefirst bit flipping occurs when the first bit and the second bit of onebit sequence have the first binary digit (e.g., “1”) and the secondbinary digit (e.g., “0”), respectively.

Next, the control unit 1212 updates the current control gate voltageV_(LSB′) employed by the second read operation by V8 which is higherthan V7, and then controls the flash memory to perform the third readoperation upon memory cells M_0-M_K according to the updated controlgate voltage V_(LSB″). Thus, a third codeword CW_3 consisted of thirdbits of the bit sequences BS_0-BS_K is received by the receiving circuit1220. Please note that the first codeword CW_1 originally buffered inthe storage device 1222 will be overwritten by the second codeword CW_2;additionally, bits of the second codeword CW_2 buffered in the storagedevice 1222 are transmitted to the comparing unit 1216 one by one beforeoverwritten by the incoming bits of the third codeword CW_3. Thecomparing unit 1216 is further arranged for comparing bits of the secondcodeword CW_2 (i.e., second bits of the bit sequences BS_0-BS_K) andbits of the third codeword CW_3 (i.e., third bits of the bit sequencesBS_0-BS_K). The comparison result will indicate which bit position hasthe second bit flipping due to a transition from the second binary digit(e.g., “0”) to the first binary digit (e.g., “1”). The counting unit1214 is further arranged for counting the number of second bit flippingbetween the second codeword CW_2 and the third codeword CW_3. That is,the counting unit 1214 generates a second counter number N2 by countingthe number of second bit flipping between second bits and third bits ofthe bit sequences BS_0-BS_K, wherein one second bit flipping occurs whenthe second bit and the third bit of one bit sequence have the secondbinary digit (e.g., “0”) and the first binary digit (e.g., “1”),respectively.

After receiving the first counter number N1 and the second counternumber N2 generated from the counting unit 1214, the control unit 1212determines the readout information which can pass the ECC parity checkby referring to the first counter number N1 and the second counternumber N2. For example, the control unit 1212 determines the shiftingdirection DS of the control gate voltage according to the first counternumber N1 and the second counter number N2. More specifically, as can beseen from FIG. 2, the first counter number N1 represents the totalnumber of 0's newly identified due to shifting the control gate voltagefrom V7-V6, and the second counter number N2 represents the total numberof 1's newly identified due to shifting the control gate voltage fromV6-V8. Thus, the number (N2-N1) is representative of a total number of1's resulted from shifting the control gate voltage from V7-V8. In thisexemplary embodiment, (N2-N1) is greater than N1, implying that thelocal minimum of the threshold voltage distribution corresponding to thelogical “1” and “0” is located on a left side of the initial controlgate voltage V_(LSB). Based on such an observation, the control unit1212 decides the shifting direction DS accordingly. In addition, thefirst counter number N1 represents the number of memory cells whosethreshold voltage is located between V7 and V6. The number (N2-N1)represents the number of memory cells whose threshold voltage is locatedbetween V7 and V8. The first counter number N1 and number (N2-N1)represent the threshold voltage distribution of a part of the memorycells M_0-M_K.

After the shifting direction DS is determined, the control logic 1212determines a new control gate voltage according to the shiftingdirection DS. When the readout information (i.e., a new codeword)obtained from applying the new control gate voltage to the control gateof each of the memory cells M_0-M_K of the target physical page P_0passes the ECC parity check, this implies that the codeword processed bythe ECC circuit 1230 will become error-free. As the LSB data issuccessfully determined by the control unit 1212 which updates thecontrol gate voltage according to the shifting direction DS, the controlunit 1212 records the currently used control gate voltage as an initialcontrol gate voltage to be used by the next LSB read operation performedupon the physical page P_0.

However, when the readout information (i.e., a new codeword) obtainedfrom applying the new control gate voltage to the control gate of eachof the memory cells M_0-M_K of the physical page P_0 fails to pass theECC parity check, this implies that the codeword processed by the ECCcircuit 1230 still contains uncorrectable error bits, the control logic912 will determine another control gate voltage according to theshifting direction DS. Updating the control gate voltage according tothe shifting direction DS is not stopped until the codeword iserror-free or all of the error bits presented in the codeword arecorrectable. Please note that the ECC circuit (e.g., a BCH decoder) 1230has error correction capability. Therefore, the control unit 1212 is notrequired to exactly shift the control gate voltage to the optimum valueV5 according to the shifting direction DS.

In above exemplary embodiment, the control unit 1212 controls the flashmemory 1100 to perform the first read operation which utilizes theinitial control gate voltage V_(LSB), the second read operation whichutilizes the lower control gate voltage V_(LSB′), and the third readoperation which utilizes the higher control gate voltage V_(LSB″),sequentially. Therefore, the initial control gate voltage V_(LSB), thelower control gate voltage V_(LSB′) and the higher control gate voltageV_(LSB″) are applied to the control gate of each of the memory cellsM_0-M_K, sequentially. However, this is for illustrative purposes only,and is not meant to be a limitation of the present invention.

As mentioned above, the threshold voltage distribution of memory cells1110 included in the flash memory 1100 may be changed due to certainfactors such as read disturbance, write/program disturbance, and/orretention disturbance. In some situations, the threshold voltagedistribution of the memory cells may be changed to a non-uniformdistribution. FIG. 4 is a diagram illustrating the adjustment made tothe control gate voltage used for reading LSB data according to anotherembodiment of the present invention. As shown in FIG. 4, the thresholdvoltage distribution of memory cells M_0-M_K of the physical page P_1 isnot uniform. The optimal control gate voltage for reading the memorycells might be V5. In other words, the control gate voltage V5 can bedeemed as a global minimum of the threshold voltage distribution ofmemory cells. Due to the non-uniform distribution between voltagesV6-V8, however, the optimal control gate voltage V5 may not be found.Please note that each voltage difference of control gate voltages V1-V9is the minimum step size (ΔV) that the memory controller 1200 cancontrol the flash memory 1100 to adjust. According to concepts of thethreshold voltage tracking mechanism mentioned above, a first counternumber N1, a second counter number N2, and the number (N2-N1) of thememory cells of the physical page P_1 can be found, respectively. Thefirst counter number N1 represents the number of the memory cells of thephysical page P_1 whose threshold voltages are located between V6-V7.The number (N2-N1) represents the number of the memory cells of thephysical page P_1 whose threshold voltages are located between V7-V8.The first count number N1 and number (N2-N1) represent a thresholdvoltage distribution of the memory cells of the physical page P_1 whosethreshold voltages are located between V6-V8. Beside, according toconcepts of the threshold voltage tracking mechanism mentioned above,the shifting direction DS can be wrongly determined as the rightdirection, i.e. toward to a voltage higher than the initial control gatevoltage V_(LSB). Hence, updating the control gate voltage according tothe shifting direction DS is not helpful for obtaining an error-freecodeword or a correctable codeword. Since a correctable codeword can notbe obtained, the control unit 1212 adjusts the control gate voltage tovoltages (e.g. V8, V9, etc.) higher than the initial voltage V_(LSB) andobtains the corresponding readout information again and again. Afterseveral times (e.g. 3 times) of ECC fail (uncorrectable), the controlunit 1222 stops to adjust the control gate voltage according to theshifting direction DS (adjust to voltages, e.g. V8, V9, etc., higherthan the initial voltage V_(LSB)) and enters a further stage of thethreshold voltage tracking mechanism. Further details are described asbelow.

Please refer to FIG. 5 in conjunction with FIG. 6. FIG. 5 is a diagramillustrating the adjustment made to the control gate voltage used forreading LSB data of the target physical page P_1 according to anembodiment of the present invention. FIG. 6 is a diagram illustratingthe operation of determining a shifting direction of the control gatevoltage for finding a better control gate voltage used for reading LSBdata the target physical page P_1 according to an embodiment of thepresent invention. To have a minimum number of error bits presented inthe readout information of the target physical page P_1, the controlgate voltage for reading LSB data should be preferably set. Since theshifting direction DS found in the last time is not helpful for findinga correctable codeword. The control unit 1212 will increase the stepsize of the control gate voltage adjustment in the further stage of thethreshold voltage tracking mechanism for eliminating the non-uniformeffect of threshold voltage distribution. The initial control gatevoltage V_(LSB) is set to V7 by the control unit 1212, and the flashmemory 1100 performs the first read operation upon memory cells M_0-M_Kof the physical page P_1 according to the initial control gate voltageV_(LSB) and obtains a first codeword CW_1′ consisted of first bits ofthe bit sequences BS_0-BS_K. Next, the control unit 1212 updates theinitial control gate voltage V_(LSB) employed by the first readoperation by V5 which is lower than V7 with 2 minimum step size ΔV, i.e.2ΔV. The control unit 1212 controls the flash memory 1100 to perform thesecond read operation upon memory cells M_0-M_K according to the updatedcontrol gate voltage V_(LSB′). Thus, a second codeword CW_2′ consistedof second bits of the bit sequences BS_0-BS_K is received by thereceiving circuit 1220. Please note that the first codeword CW_1′ isbuffered in the storage device 1222, and bits of the first codewordCW_1′ buffered in the storage device 1222 are transmitted to thecomparing unit 1216 one by one before overwritten by the incoming bitsof the second codeword CW_2′. The comparing unit 1216 is arranged forcomparing bits of the first codeword CW_1′ (i.e., first bits of the bitsequences BS_0-BS_K) and bits of the second codeword CW_2′ (i.e., secondbits of the bit sequences BS_0-BS_K). The comparison result willindicate which bit position has one first bit flipping due to atransition from a first binary digit (e.g., “1”) to a second binarydigit (e.g., “0”). The counting unit 1214 is coupled to the comparingunit 1216 and the control unit 1212, and is arranged for counting thenumber of first bit flipping between the first codeword CW_1′ and thesecond codeword CW_2′. That is, the counting unit 1214 generates a firstcounter number A1 by counting the number of first bit flipping betweenfirst bits and second bits of the bit sequences BS_0-BS_K, wherein onefirst bit flipping occurs when the first bit and the second bit of onebit sequence have the first binary digit (e.g., “1”) and the secondbinary digit (e.g., “0”), respectively.

Next, the control unit 1212 updates the current control gate voltageV_(LSB′) employed by the second read operation by V9 which is higherthan V7 with 2 minimum step size ΔV (i.e. 2ΔV), and then controls theflash memory to perform the third read operation upon memory cellsM_0-M_K according to the updated control gate voltage V_(LSB″). Thus, athird codeword CW_3′ consisted of third bits of the bit sequencesBS_0-BS_K is received by the receiving circuit 1220. Please note thatthe first codeword CW_1′ originally buffered in the storage device 1222will be overwritten by the second codeword CW_2′; additionally, bits ofthe second codeword CW_2′ buffered in the storage device 1222 aretransmitted to the comparing unit 1216 one by one before overwritten bythe incoming bits of the third codeword CW_3′. The comparing unit 1216is further arranged for comparing bits of the second codeword CW_2′(i.e., second bits of the bit sequences BS_0-BS_K) and bits of the thirdcodeword CW_3′ (i.e., third bits of the bit sequences BS_0-BS_K). Thecomparison result will indicate which bit position has the second bitflipping due to a transition from the second binary digit (e.g., “0”) tothe first binary digit (e.g., “1”). The counting unit 1214 is furtherarranged for counting the number of second bit flipping between thesecond codeword CW_2′ and the third codeword CW_3′. That is, thecounting unit 1214 generates a second counter number A2 by counting thenumber of second bit flipping between second bits and third bits of thebit sequences BS_0-BS_K, wherein one second bit flipping occurs when thesecond bit and the third bit of one bit sequence have the second binarydigit (e.g., “0”) and the first binary digit (e.g., “1”), respectively.

After receiving the first counter number A1 and the second counternumber A2 generated from the counting unit 1214, the control unit 1212determines the readout information which can pass the ECC parity checkby referring to the first counter number A1 and the second counternumber A2. For example, the control unit 1212 determines the shiftingdirection DS of the control gate voltage according to the first counternumber A1 and the second counter number A2. More specifically, as can beseen from FIG. 5, the first counter number A1 represents the totalnumber of 0's newly identified due to shifting the control gate voltagefrom V7 to V5, and the second counter number A2 represents the totalnumber of 1's newly identified due to shifting the control gate voltagefrom V5 to V9. Thus, the number (A2-A1) is representative of a totalnumber of 1's resulted from shifting the control gate voltage from V7 toV9. In this exemplary embodiment, (A2-A1) is greater than A1, implyingthat the local minimum of the threshold voltage distributioncorresponding to logical “1” and “0” is located on a left side of theinitial control gate voltage V_(LSB). Based on such an observation, thecontrol unit 1212 decides the shifting direction DS accordingly. Inaddition, the first counter number A1 represents the number of memorycells whose threshold voltages are located between V7 and V5. The number(A2-A1) represents the number of memory cells whose threshold voltagesare located between V7 and V9. The first counter number A1 and number(A2-A1) represent the threshold voltage distribution of a part of thememory cells M_0-M_K of the physical page P_1. Please note that, thethreshold voltage distribution obtained with the minimum step size ΔV(referring to FIG. 4) and the threshold voltage distribution obtainedwith twice the minimum step size 2ΔV (referring to FIG. 5) aredifferent. The threshold voltage distribution obtained with 2ΔV (socalled the second threshold voltage distribution) is smoother than thethreshold voltage distribution obtained with ΔV (so called the firstthreshold voltage distribution). The first threshold voltagedistribution represents threshold voltages of a first group of memorycells whose threshold voltages are located between V6 and V8. The secondthreshold voltage distribution represents threshold voltages of a secondgroup of memory cells whose threshold voltages are located between V5and V9. The first group of the memory cells comprises the second groupof the memory cells.

The determination of step size used for control gate voltage adjustmentcan be referred to the program/erase count (P/E cycles) of the memorycells to be read. Generally speaking, memory cells having higher P/Ecycles will suffer a worse non-uniform threshold voltage effect. Thestep size should be increased correspondingly for eliminating theeffect. The control unit 1212 can find out a program/erase count of thetarget memory cells from a lookup table in the control logic 1210 anddetermine the step size of control gate voltage adjustment used in thethreshold voltage tracking mechanism accordingly. Please note that thestep size can be determined according to other characteristic of thetarget memory cells.

After the correct shifting direction DS obtained according to the secondthreshold voltage distribution is determined, the control logic 1212determines a new control gate voltage according to the correct shiftingdirection DS. A correctable codeword can be found according to thecorrect shifting direction DS. The mechanism for obtaining thecorrectable codeword according to the correct shifting direction DS issimilar to illustration mentioned above (please refer to FIG. 2 and FIG.3 and related illustrations). Hence, further illustration is omitted.

FIG. 7A is a diagram illustrating the adjustment made to the controlgate voltage used for reading LSB data according to an embodiment of thepresent invention. Due to change of the threshold voltage distribution,the threshold voltages of some memory cells each originally programmedto store LSB=1 are distributed in the voltage region V5-V11, and thethreshold voltages of some memory cells each originally programmed tostore LSB=0 are distributed in the voltage region V1-V5. To have aminimum number of error bits presented in the readout information of thetarget physical page P_2, the control gate voltage for reading LSB datashould be preferably set by V5 shown in FIG. 7A. When the initialcontrol gate voltage V_(LSB0) is set to V7 by the control unit 1212 andthe flash memory 1100 performs the first read operation upon memorycells M_0-M_K of physical page P_2 according to the initial control gatevoltage V_(LSB0), the number of error bits presented in the readoutinformation (i.e., a first codeword CW_1 consisted of first bits of thebit sequences BS_0-BS_K) exceeds the maximum number of error bits thatcan be corrected by the ECC circuit 1230. Thus, the threshold voltagetracking mechanism is enabled accordingly. Next, the control unit 1212updates the initial control gate voltage V_(LSB0) employed by the firstread operation by V6 (V_(LSB1)) which is lower than V7 with a minimumstep size (ΔV) that the memory controller 1200 can control the flashmemory 1100 to adjust. Then the control unit 1212 controls the flashmemory to perform the second read operation upon memory cells M_0-M_K ofphysical page P_2 according to the updated control gate voltageV_(LSB1). Thus, a second codeword CW_2 consisted of second bits of thebit sequences BS_0-BS_K is received by the receiving circuit 1220.Please note that the first codeword CW_1 is buffered in the storagedevice 1222, and bits of the first codeword CW_1 buffered in the storagedevice 1222 are transmitted to the comparing unit 1216 one by one beforeoverwritten by the incoming bits of the second codeword CW_2. Thecomparing unit 1216 is arranged for comparing bits of the first codewordCW_1 (i.e., first bits of the bit sequences BS_0-BS_K) and bits of thesecond codeword CW_2 (i.e., second bits of the bit sequences BS_0-BS_K).The comparison result will indicate which bit position has one first bitflipping due to a transition from a first binary digit (e.g., “1”) to asecond binary digit (e.g., “0”). The counting unit 1214 is coupled tothe comparing unit 1216 and the control unit 1212, and is arranged forcounting the number of first bit flipping between the first codewordCW_1 and the second codeword CW_2. That is, the counting unit 1214generates a first counter number B1 by counting the number of first bitflipping between first bits and second bits of the bit sequencesBS_0-BS_K, wherein one first bit flipping occurs when the first bit andthe second bit of one bit sequence have the first binary digit (e.g.,“1”) and the second binary digit (e.g., “0”), respectively.

Next, the control unit 1212 updates the current control gate voltageV_(LSB1) employed by the second read operation by V8 which is higherthan V7, and then controls the flash memory to perform the third readoperation upon memory cells M_0-M_K of physical page P_2 according tothe updated control gate voltage V_(LSB2) Thus, a third codeword CW_3consisted of third bits of the bit sequences BS_0-BS_K of physical pageP_2 is received by the receiving circuit 1220. Please note that thefirst codeword CW_1 originally buffered in the storage device 1222 willbe overwritten by the second codeword CW_2; additionally, bits of thesecond codeword CW_2 buffered in the storage device 1222 are transmittedto the comparing unit 1216 one by one before overwritten by the incomingbits of the third codeword CW_3. The comparing unit 1216 is furtherarranged for comparing bits of the second codeword CW_2 (i.e., secondbits of the bit sequences BS_0-BS_K) and bits of the third codeword CW_3(i.e., third bits of the bit sequences BS_0-BS_K). The comparison resultwill indicate which bit position has the second bit flipping due to atransition from the second binary digit (e.g., “0”) to the first binarydigit (e.g., “1”). The counting unit 1214 is further arranged forcounting the number of second bit flipping between the second codewordCW_2 and the third codeword CW_3. That is, the counting unit 1214generates a second counter number B2 by counting the number of secondbit flipping between second bits and third bits of the bit sequencesBS_0-BS_K, wherein one second bit flipping occurs when the second bitand the third bit of one bit sequence have the second binary digit(e.g., “0”) and the first binary digit (e.g., “1”), respectively.

As can be seen from FIG. 7A, the first counter number B1 represents thetotal number of 0's newly identified due to shifting the control gatevoltage from V7 to V6, and the second counter number B2′ represents thetotal number of 1's newly identified due to shifting the control gatevoltage from V6 to V8. Thus, the number (B2′-B1) is representative of atotal number of 1's resulted from shifting the control gate voltage fromV7 to V8. The first counter number B1 maps to the control gate voltageregion V7-V6 and represents the number of memory cells whose thresholdvoltages are located between the voltage region V7-V6. The number(B2′-B1), illustrated as B2 in FIG. 7A, maps to the control gate voltageregion V7-V8 and represents the number of memory cells whose thresholdvoltages are located between the voltage region V7-V8. Under theteaching of the present embodiment, people skill in the art can readilyunderstand how to adjust the control gate voltage from V_(LSB3),V_(LSB4), V_(LSB5), V_(LSB6), V_(LSB7) to V_(LSB8) and obtain thenumbers (B3, B4, B5, B6, B7, and B8) mapping to each particular controlgate voltage region by the control logic 1210. Hence, furtherillustrations are omitted. Please note that the set of number B1, B2,B3, B4, B5, B6, B7, and B8 and the corresponding mapping relations withthe particular control gate voltage ranges can be deemed as a firstthreshold voltage distribution of the memory cells whose thresholdvoltages are located between V3 to V11 and can be stored in the controllogic 1210. The number of adjusting the control gate voltages in thepresent embodiment is only an example rather than a limitation. Peopleskill in the art can determine the number of adjusting the control gatevoltages as required.

Please refer to FIG. 7B in conjunction with FIG. 7A. FIG. 7B is adiagram showing a threshold voltage distribution obtained from averagingthe threshold voltage distribution shown in FIG. 7A. Since the thresholdvoltage distribution shown in FIG. 7A (the first threshold voltagedistribution) is not uniform, utilizing the first threshold voltagedistribution to determining a control gate voltage for performing a readoperation upon the physical page P_2 may not obtain a correctablecodeword. Hence, the control logic performs an average operation uponthe first threshold voltage distribution for eliminating the non-uniformeffect and obtains a smoother threshold voltage distribution (a secondthreshold voltage distribution). Further details are described asfollows.

As shown in FIG. 7B, the second threshold voltage distribution comprisesa set of number C1, C2, C3, C4, C5, and C6. Each number maps to aparticular control gate voltage region. The number C1 maps to thecontrol gate voltage region V7-V6 and represents the number of memorycells whose threshold voltages are located between the voltage regionV7-V6. Similarly, the number C2 maps to the control gate voltage regionV7-V8 and represents the number of memory cells whose threshold voltagesare located between the voltage region V7-V8, and so on. The controllogic 1210 obtains the number C1 by averaging B1, B2, and B3. In thefirst threshold voltage distribution, the number B1 maps to voltageregion V6-V7. The voltage region mapping relation of the number B1 isthe same as the voltage region mapping relation of the number C1. Thenumber B2 maps to voltage region V7-V8, i.e. a voltage range neighboringto voltage region of the number C1 (i.e. V6-V7). The number B3 maps tovoltage region V5-V6, i.e. another voltage range neighboring to voltageregion of the number C1 (i.e. V6-V7). The number C2, C3, C4, C5, and C6can be obtained by the control logic 1210 in a similar way.

Please note that a smoother second threshold voltage distribution can beobtained from the first threshold voltage distribution in many waysdifferent from the embodiment illustrated above. For example, the numberC1 can be obtained by averaging the numbers B1-B5, B1-B2, or B1 and B3.Alternatively, the control logic 1210 can perform a running sumoperation upon the numbers B1-B8 to obtain the numbers C1-C6. Forexample, the number C1 can be obtained by summing the numbers B1-B3. Thenumber C2 can be obtained by summing the numbers B1, B2, and B4, and soon. Please note that the second threshold voltage distribution can bedetermined by performing an average operation or a running sum operationupon the first threshold voltage operation. In other words, the secondthreshold voltage distribution is obtained by processing the information(e.g. number of memory cells and mapping relations) of the firstthreshold voltage distribution.

In addition, please refer to FIG. 7C in conjunction with FIG. 7A. FIG.7C is a diagram showing a threshold voltage distribution obtained fromselecting a part of information of the threshold voltage distributionshown in FIG. 7A. A smoother threshold voltage distribution can beobtained from selecting a part of information of the first thresholdvoltage distribution. As shown in FIG. 7C, a smoother second thresholdvoltage distribution comprises a set of number D1, D2, D3, and D4. Eachnumber maps to a particular control gate voltage region. The number D1maps to the control gate voltage region V7-V6 and represents the numberof memory cells whose threshold voltages are located between the voltageregion V7-V6. Similarly, the number D2 maps to the control gate voltageregion V8-V9 and represents the number of memory cells whose thresholdvoltages are located between the voltage region V8-V9, and so on. Thecontrol logic 1210 obtains the number D1 and the mapping relation byselecting B1 as D1. The control logic 1210 obtains the number D2 and themapping relation by selecting B4 as D2, and so on. The set of number B1,B4, B5, and B8 can be selected by a discontinuous voltage spacing fromthe first threshold voltage distribution.

For obtaining a further smoothing threshold voltage distribution, a stepsize for obtaining the first threshold voltage can be also adjusted. Inother words, the control logic 1210 can adjust the step size forobtaining the first threshold voltage distribution according to theconcept illustrated in FIG. 5 and related illustrations and smooth thefirst threshold voltage distribution for obtaining the second thresholdvoltage distribution according to the concept illustrated in the aboveembodiments.

As shown in FIG. 7B and FIG. 7C, the second threshold voltagedistribution is smooth and uniform. The control logic 1210 can obtain acorrect shifting direction DS from the second threshold voltagedistribution. The concept of obtaining the correct shifting directionaccording to the threshold voltage distribution is similar to the aboveembodiments. Hence, further illustrations are omitted.

After the correct shifting direction DS obtained according to the secondthreshold voltage distribution is determined, the control logic 1212determines a new control gate voltage for performing a read operationupon the physical page P_2 according to the correct shifting directionDS. A correctable codeword can be found according to the correctshifting direction DS. The mechanism for obtaining the correctablecodeword according to the correct shifting direction DS is similar toillustration mentioned above (please refer to FIG. 2 and FIG. 3 andrelated illustrations). Hence, further illustration is omitted.

Alternatively, the control logic 1212 can determines a new control gatevoltage for performing a read operation upon the physical page P_2according to a minimum number of the second threshold voltagedistribution. For example, the minimum number of the second thresholdvoltage distribution shown in FIG. 7B is C5. Hence, the control logic1212 can determine a new control gate voltage for performing the readoperation upon the physical page P_2 according to the voltage regionthat the number C5 mapped to. The number C5 maps to the voltage regionV4-V5. The new control gate voltage can be determined as V4 or V5 orother voltages neighboring to voltage region V4-V5.

FIG. 8 is a flow chart illustrating a concept of the present invention.The order of the steps in the following flow is an exemplary embodimentof the present invention rather than a limitation. The flow 800comprises the flowing steps:

-   -   Step 810: controlling a flash memory to perform a first read        operation upon a part of the memory cells according to an        initial control gate voltage;    -   Step 820: controlling the flash memory to perform a plurality of        read operations upon the part of the memory cells while readout        information of the first read operation was uncorrectable;    -   Step 830: obtaining a first threshold voltage distribution        according to readout information of the plurality of read        operations;    -   Step 840: smoothing the first threshold voltage distribution for        obtaining a second threshold voltage distribution; and    -   Step 850: controlling the flash memory to perform a second read        operation upon the part of the memory cells according to the        second threshold voltage distribution.

In Step 810, the control logic 1210 controls the flash memory 1100 toperform a first read operation upon a part of the memory cells of flashmemory 1100, e.g. physical page P_1, according to an initial controlgate voltage, e.g. V_(LSB0). While readout information of the first readoperation was uncorrectable, in step 820, the control logic 1210controls the flash memory 1100 to perform a plurality of read operationsupon the physical page P_1. Since the readout information isuncorrectable, a better control gate voltage should be found forperforming the read operation and obtaining correct (correctable)readout information. In step 830, the control logic 1210 obtains a firstthreshold voltage distribution according to readout information of theplurality of read operations. However, the first threshold voltagedistribution may be non-uniform. Hence, in step 840, the first thresholdvoltage distribution should be processed by the control logic 1210 forobtaining a smoother second threshold voltage distribution. Since thesecond threshold voltage distribution is obtained, a shifting directionfor adjusting the control gate voltage can be determined accordingly, ora better control gate voltage can be obtained according to a minimumvalue of the second threshold voltage distribution. In step 850, thecontrol logic 1210 controls the flash memory 1100 to perform a secondread operation upon the physical page P_1 according to the secondthreshold voltage distribution. Hence, correct (or correctable) readoutinformation can be obtained.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A method for reading data stored in a flashmemory, wherein the flash memory comprises a first set of memory cellsand a second set of memory cells, and each memory cell corresponds to aparticular threshold voltage, the method comprising: measuring a firstvoltage characteristic of the first set of the memory cells; measuring asecond voltage characteristic of the second set of the memory cells; andreading the first set of the flash memory by using the second voltagecharacteristic.
 2. The method as claimed in claim 1, wherein the firstvoltage characteristic is different from the second voltagecharacteristic, and the first set of memory cells comprises at least apart of the memory cells of the second set.
 3. A memory controller forreading data stored in a flash memory, wherein the flash memorycomprises a first set of memory cells and a second set of memory cells,and each memory cell corresponds to a particular threshold voltage, thememory controller comprising: a control logic, measuring a first voltagecharacteristic of the first set of the memory cells, measuring a secondvoltage characteristic of the second set of the memory cells, andreading the first set of the flash memory by using the second voltagecharacteristic.
 4. The memory controller as claimed in claim 3, whereinthe first voltage characteristic is different from the second voltagecharacteristic, and the first set of memory cells comprises at least apart of the memory cells of the second set.
 5. A method for reading datastored in a flash memory, wherein the flash memory comprises a pluralityof memory cells and each memory cell has a particular threshold voltage,the method comprising: reading a part of the memory cells of the flashmemory by a first control gate voltage; detecting error bits of thememory cells; correcting the error bits of the memory cell by readingthe flash memory continuously; reading the flash memory for measuring afirst voltage characteristic of the memory cells; averaging the firstvoltage characteristic for obtaining a second voltage characteristic;and reading a part of the flash memory again by using the second voltagecharacteristic.
 6. A system for reading data stored in a flash memory,wherein the flash memory comprises a plurality of memory cells and eachmemory cell has a particular threshold voltage, the system comprising: acontrol logic for reading a part of the memory cells of the flash memoryby using a first control gate voltage; a detector for detecting errorbits of the memory cells; a corrector for correcting the error bits ofthe memory cell by reading the flash memory continuously; wherein thecontrol logic further obtains a first voltage characteristic of thememory cells by reading the flash memory, averages the first voltagecharacteristic for obtaining a second voltage characteristic, and readsa part of the flash memory again by using the second voltagecharacteristic.